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| MCP6H01/2/4 1.2 MHz, 16V Op Amps Features: * * * * * * Input Offset Voltage: 0.7 mV (typical) Quiescent Current: 135 A (typical) Common Mode Rejection Ratio: 100 dB (typical) Power Supply Rejection Ratio: 102 dB (typical) Rail-to-Rail Output Supply Voltage Range: - Single-Supply Operation: 3.5V to 16V - Dual-Supply Operation: 1.75V to 8V Gain Bandwidth Product: 1.2 MHz (typical) Slew Rate: 0.8V/s (typical) Unity Gain Stable Extended Temperature Range: -40C to +125C No Phase Reversal Description: Microchip's MCP6H01/2/4 family of operational amplifiers (op amps) has a wide supply voltage range of 3.5V to 16V and rail-to-rail output operation. This family is unity gain stable and has a gain bandwidth product of 1.2 MHz (typical). These devices operate with a single-supply voltage as high as 16V, while only drawing 135 A/amplifier (typical) of quiescent current. The MCP6H01/2/4 family is offered in single (MCP6H01), dual (MCP6H02) and quad (MCP6H04) configurations. All devices are fully specified in extended temperature range from -40C to +125C. * * * * * Package Types MCP6H01 SOIC NC 1 VIN- 2 VIN+ 3 VSS 4 8 NC 7 VDD 6 VOUT 5 NC Applications: * * * * Automotive Power Electronics Industrial Control Equipment Battery Powered Systems Medical Diagnostic Instruments MCP6H02 SOIC VOUTA 1 VINA- 2 VINA+ 3 VSS 4 8 VDD 7 VOUTB 6 VINB- 5 VINB+ Design Aids: * * * * * SPICE Macro Models FilterLab(R) Software MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes MCP6H01 2x3 TDFN NC 1 VIN- 2 VIN+ 3 VSS 4 EP 9 8 NC 7 VDD 5 NC MCP6H02 2x3 TDFN VOUTA 1 EP 9 8 VDD 7 VOUTB 6 VINB- 5 VINB+ VINA- 2 6 VOUT VINA+ 3 VSS 4 Typical Application R1 V1 VDD MCP6H01 VOUT R2 VREF MCP6H04 SOIC, TSSOP VOUTA 1 VINA- 2 VINA+ 3 VDD 4 VINB+ 5 VINB- 6 VOUTB 7 14 VOUTD 13 VIND- 12 VIND+ 11 VSS 10 VINC+ 9 VINC- 8 VOUTC V2 R1 R2 * Includes Exposed Thermal Pad (EP); see Table 3-1. Difference Amplifier (c) 2011 Microchip Technology Inc. DS22243C-page 1 MCP6H01/2/4 NOTES: DS22243C-page 2 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 1.0 1.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See 4.1.2 "Input Voltage Limits". VDD - VSS..........................................................................17V Current at Input Pins......................................................2 mA Analog Inputs (VIN+, VIN-).............VSS - 1.0V to VDD + 1.0V All Other Inputs and Outputs ............VSS - 0.3V to VDD + 0.3V Difference Input Voltage..........................................VDD - VSS Output Short-Circuit Current...................................continuous Current at Output and Supply Pins ..............................65 mA Storage Temperature.....................................-65C to +150C Maximum Junction Temperature (TJ)...........................+150C ESD protection on all pins (HBM; MM)................... 2 kV; 200V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V, VSS = GND, TA = +25C, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2 and RL = 10 k to VL. (Refer to Figure 1-1). Parameters Input Offset Input Offset Voltage Input Offset Drift with Temperature Power Supply Rejection Ratio Input Bias Current and Impedance Input Bias Current IB IB IB Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common Mode Input Voltage Range Common Mode Rejection Ratio VCMR CMRR VSS - 0.3 78 82 84 Open-Loop Gain DC Open-Loop Gain (Large Signal) AOL 95 115 -- dB 0.2V < VOUT <(VDD-0.2V) -- 93 98 100 VDD - 2.3 -- -- -- V dB dB dB VCM = -0.3V to 1.2V, VDD = 3.5V VCM = -0.3V to 2.7V, VDD = 5V VCM = -0.3V to 12.7V, VDD = 15V IOS ZCM ZDIFF -- -- -- -- -- -- 10 600 10 1 1013||6 1013||6 -- -- 25 -- -- -- pA pA nA pA ||pF ||pF TA = +85C TA = +125C VOS VOS/TA PSRR -3.5 -- 87 0.7 2.5 102 +3.5 -- -- mV V/C TA = -40C to +125C dB Sym Min Typ Max Units Conditions (c) 2011 Microchip Technology Inc. DS22243C-page 3 MCP6H01/2/4 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V, VSS = GND, TA = +25C, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2 and RL = 10 k to VL. (Refer to Figure 1-1). Parameters Output High-Level Output Voltage VOH 3.490 4.985 14.970 Low-Level Output Voltage VOL -- -- -- Output Short-Circuit Current ISC -- -- -- Power Supply Supply Voltage Quiescent Current per Amplifier VDD IQ 3.5 1.75 -- -- -- -- -- 125 130 135 16 8 175 180 185 V V A A A Single-supply operation Dual-supply operation IO = 0, VDD = 3.5V VCM = VDD/4 IO = 0, VDD = 5V VCM = VDD/4 IO = 0, VDD = 15V VCM = VDD/4 3.495 4.993 14.980 0.005 0.007 0.020 27 45 50 -- -- -- 0.010 0.015 0.030 -- -- -- V V V V V V mA mA mA VDD = 3.5V 0.5V input overdrive VDD = 5V 0.5V input overdrive VDD = 15V 0.5V input overdrive VDD = 3.5V 0.5 V input overdrive VDD = 5V 0.5 V input overdrive VDD = 15V 0.5 V input overdrive VDD = 3.5V VDD = 5V VDD = 15V Sym Min Typ Max Units Conditions AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. (Refer to Figure 1-1). Parameters AC Response Gain Bandwidth Product Phase Margin Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- -- 12 35 30 1.9 -- -- -- -- Vp-p nV/Hz nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 1 kHz f = 10 kHz f = 1 kHz GBWP PM SR -- -- -- 1.2 57 0.8 -- -- -- MHz C V/s G = +1V/V Sym Min Typ Max Units Conditions DS22243C-page 4 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V and VSS = GND. Parameters Temperature Ranges Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-2x3 TDFN Thermal Resistance, 8L-SOIC Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP JA JA JA JA -- -- -- -- 41 149.5 95.3 100 -- -- -- -- C/W C/W C/W C/W TA TA -40 -65 -- -- +125 +150 C C Note 1 Sym Min Typ Max Units Conditions Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150C. 1.2 Test Circuits CF 6.8 pF RG 100 k VP VIN+ MCP6H0X VIN- VM RG 100 k RF 100 k CF 6.8 pF RL 10 k VOUT CL 60 pF CB1 100 nF RF 100 k VDD VDD/2 The circuit used for most DC and AC tests is shown in Figure 1-1. This circuit can independently set VCM and VOUT (refer to Equation 1-1). Note that VCM is not the circuit's common mode voltage ((VP + VM)/2), and that VOST includes VOS plus the effects (on the input offset error, VOST) of temperature, CMRR, PSRR and AOL. EQUATION 1-1: G DM = RF RG V CM = ( V P + V DD 2 ) 2 VOST = VIN- - VIN+ VOUT = ( V DD 2 ) + ( V P - V M ) + V OST ( 1 + G DM ) Where: GDM = Differential Mode Gain VCM = Op Amp's Common Mode Input Voltage VOST = Op Amp's Total Input Offset Voltage (V/V) (V) (mV) CB2 1 F VL FIGURE 1-1: AC and DC Test Circuit for Most Specifications. (c) 2011 Microchip Technology Inc. DS22243C-page 5 MCP6H01/2/4 NOTES: DS22243C-page 6 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 21% Percentage of Occurences 18% 15% 12% 9% 6% 3% 0% -2.5 -2.0 -1.5 1.0 -3.0 -1.0 -0.5 Input Offset Voltage (mV) 3.0 0.0 0.5 1.5 2.0 2.5 Input Offset Voltage (V) 2550 Samples 1000 TA = +125C 800 TA = +85C 600 TA = +25C TA = -40C 400 200 0 -200 -400 VDD = 5V -600 Representative Part -800 -1000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Common Mode Input Voltage (V) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -0.5 35% Percentage of Occurences Input Offset Voltage (V) 30% 25% 20% 15% 10% 5% 0% -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 Input Offset Voltage Drift (V/C) 2550 Samples TA = - 40C to +125C TA = +125C TA = +85C TA = +25C TA = -40C VDD = 15V Representative Part 1.5 3.5 5.5 7.5 9.5 11.5 13.5 15.5 Common Mode Input Voltage (V) FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 0 2 4 6 8 10 12 Output Voltage (V) 14 16 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -0.5 Input Offset Voltage (V) Input Offset Voltage (V) TA = +125C TA = +85C TA = +25C TA = -40C Representative Part VDD = 15V VDD = 5V VDD = 3.5V Representative Part VDD = 3.5V 0.0 0.5 1.0 1.5 2.0 Common Mode Input Voltage (V) 2.5 FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-6: Output Voltage. Input Offset Voltage vs. (c) 2011 Microchip Technology Inc. DS22243C-page 7 MCP6H01/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 0 2 120 110 100 90 80 70 60 50 40 30 20 10 10 100 100 1k 10k 1000 10000 Frequency (Hz) 100k 1M 100000 1000000 PSRR+ Input Offset Voltage (V) Representative Part CMRR CMRR, PSRR (dB) PSRR- TA = TA = TA = TA = +125C +85C +25C -40C Representative Part 4 6 8 10 12 14 Power Supply Voltage (V) 16 18 FIGURE 2-7: Input Offset Voltage vs. Power Supply Voltage. 1,000 Input Noise Voltage Density (nV/ Hz) FIGURE 2-10: Frequency. 130 120 CMRR, PSRR (dB) 110 100 90 80 70 60 50 CMRR, PSRR vs. PSRR 100 CMRR @ VDD = 15V @ VDD = 5V @ VDD = 3.5V 10 1 1 10 10 100 1k 100 1000 Frequency (Hz) 10k 10000 100k 100000 -50 -25 0 25 50 75 100 125 Ambient Temperature (C) FIGURE 2-8: vs. Frequency. 50 Input Noise Voltage Density (nV/ Hz) 45 40 35 30 25 20 15 10 -1 1 f = 1 kHz VDD = 16V Input Noise Voltage Density FIGURE 2-11: Temperature. Input Bias and Offset Currents (A) 100000 100n VDD = 15V CMRR, PSRR vs. Ambient 10000 10n Input Bias Current 1000 1n 100 100p 10 10p Input Offset Current 1 1p 105 35 45 55 65 75 85 95 115 Ambient Temperature (C) 125 25 3 5 7 9 11 13 Common Mode Input Voltage (V) 15 FIGURE 2-9: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: Input Bias, Offset Currents vs. Ambient Temperature. DS22243C-page 8 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 100n 100000 TA = +125C 120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20 0 2 4 6 8 10 12 14 Common Mode Input Voltage (V) 16 1.0E-01 0 Open-Loop Gain Input Bias Current (A) -60 Open-Loop Phase 1n 1000 100p 100 10p 10 1p 1 TA = +85C VDD = 15V -90 -120 -150 -180 0.1 1.0E+00 1 1.0E+01 10 100 1k 10k 100k 1M 10M Frequency (Hz) 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 -210 FIGURE 2-13: Input Bias Current vs. Common Mode Input Voltage. 200 190 180 170 160 150 140 130 120 110 100 90 80 -50 -25 FIGURE 2-16: Frequency. 160 Open-Loop Gain, Phase vs. VDD = 15V VDD = 5V VDD = 3.5V DC-Open Loop Gain (dB) 150 140 130 120 110 100 90 80 3 5 7 9 11 13 Power Supply Voltage (V) 15 17 VSS + 0.2V < VOUT < VDD - 0.2V Quiescent Current (A/Amplifier) 0 25 50 75 100 Ambient Temperature (C) 125 FIGURE 2-14: Quiescent Current vs. Ambient Temperature. 200 180 160 140 120 100 80 60 40 20 0 0 2 FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. 150 DC-Open Loop Gain (dB) 140 130 120 110 100 90 80 0.00 0.05 0.10 0.15 0.20 0.25 0.30 VDD = 15V VDD = 5V VDD = 3.5V Quiescent Current (A/Amplifier) TA = +125C TA = +85C TA = +25C TA = -40C 4 6 8 10 12 Power Supply Voltage (V) 14 16 Output Voltage Headroom (V) VDD - VOH or VOL - VSS FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. (c) 2011 Microchip Technology Inc. DS22243C-page 9 Open-Loop Phase () 10n 10000 -30 MCP6H01/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. Output Short Circuit Current (mA) 160 Channel to Channel Separation (dB) 140 120 100 80 60 40 100 100 Input Referred 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 16 Power Supply Voltage (V) TA = +125C TA = +85C TA = +25C TA = -40C 1k 10k 1000 10000 Frequency (Hz) 100k 100000 FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6H02 only). 1.8 Gain Bandwidth Product (MHz) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 VDD = 3.5V Phase Margin Gain Bandwidth Product FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. 100 Output Voltage Swing (VP-P) VDD = 15V 180 160 Phase Margin () 140 120 100 80 60 40 20 0 -25 0 25 50 75 100 125 Ambient Temperature (C) 10 VDD = 5V VDD = 3.5V 1 0.1 100 100 1k 1000 10k 100k 10000 100000 Frequency (Hz) 1M 1000000 FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 1.8 Gain Bandwidth Product (MHz) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 VDD = 15V Phase Margin Gain Bandwidth Product FIGURE 2-23: Frequency. Output Voltage Headroom (mV) 10000 Output Voltage Swing vs. 180 160 120 100 80 60 40 20 0 -25 0 25 50 75 100 125 Ambient Temperature (C) Phase Margin () 140 VDD = 15V 1000 VDD - VOH 100 10 VOL - VSS 1 0.01 0.1 1 10 Output Current (mA) 100 FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-24: Output Voltage Headroom vs. Output Current. DS22243C-page 10 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +3.5V to +16V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. Output Voltage Headroom (mV) Output Voltage Headroom (mV) 1000 VDD = 5V 8 7 6 5 4 3 2 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 VOL - VSS VDD = 5V VDD - VOH 100 VDD - VOH 10 VOL - VSS 1 0.1 0.01 0.1 1 10 Output Current (mA) 100 FIGURE 2-25: Output Voltage Headroom vs. Output Current. Output Voltage Headroom (mV) 1000 VDD = 3.5V FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. Output Voltage Headroom (mV) 8 7 6 5 4 VOL - VSS VDD - VOH 100 10 1 VDD - VOH VOL - VSS 3 2 -50 -25 VDD = 3.5V 0.1 0.0 0.1 1.0 Output Current (mA) 10.0 0 25 50 75 Ambient Temperature (C) 100 125 FIGURE 2-26: Output Voltage Headroom vs. Output Current. Output Voltage Headroom (mV) 22 21 20 19 18 17 16 15 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 VOL - VSS VDD = 15V VDD - VOH FIGURE 2-29: Output Voltage Headroom vs. Ambient Temperature. 1.0 0.9 Slew Rate (V/s) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 Falling Edge, VDD = 15V Rising Edge, VDD = 15V FIGURE 2-27: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-30: Temperature. Slew Rate vs. Ambient (c) 2011 Microchip Technology Inc. DS22243C-page 11 MCP6H01/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +3.5 V to +16 V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 1.6 1.4 Slew Rate (V/s) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 Falling Edge, VDD = 3.5V Rising Edge, VDD = 3.5V Falling Edge, VDD = 5V Rising Edge, VDD = 5V 16 14 Output Voltage (V) 12 10 8 6 4 2 0 Time (20 s/div) VDD = 15V G = +1V/V FIGURE 2-31: Temperature. Slew Rate vs. Ambient FIGURE 2-34: Pulse Response. 16 Large Signal Non-Inverting Output Voltage (20 mv/div) 14 Output Voltage (V) 12 10 8 6 4 2 Time (2 s/div) 0 Time (20 s/div) VDD = 15V G = -1V/V VDD = 15V G = +1V/V FIGURE 2-32: Pulse Response. Small Signal Non-Inverting FIGURE 2-35: Response. 17 Large Signal Inverting Pulse Output Voltage (20 mv/div) Output Voltage (V) VDD = 15V G = -1V/V 15 13 11 9 7 5 3 1 -1 VDD = 15V G = +2V/V VIN VOUT Time (2 s/div) Time (0.1 ms/div) FIGURE 2-33: Response. Small Signal Inverting Pulse FIGURE 2-36: The MCP6H01/2/4 Shows No Phase Reversal. DS22243C-page 12 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +3.5 V to +16 V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 1000 Closed Loop Output Impedance () 1m 1.00E-03 100 1.00E-04 10 1.00E-05 100 -IIN (A) 1.00E-06 1 TA = +125C TA = +85C TA = +25C TA = -40C 100n 1.00E-07 10n 1.00E-08 1.00E-09 10 G N: 101V/V 11V/V 1V/V 1n 100p 1.00E-10 10p 1.00E-11 1.00E-12 1 1p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 VIN (V) 1.0E+01 10 1.0E+02 100 1k 10k Frequency (Hz) 1.0E+03 1.0E+04 1.0E+05 100k 1.0E+06 1M FIGURE 2-37: Closed Loop Output Impedance vs. Frequency. FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS). (c) 2011 Microchip Technology Inc. DS22243C-page 13 MCP6H01/2/4 NOTES: DS22243C-page 14 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP6H01 SOIC 6 2 3 7 -- -- -- -- -- -- 4 -- -- -- 1, 5, 8 -- PIN FUNCTION TABLE MCP6H02 SOIC 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- -- 2x3 TDFN 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- 9 MCP6H04 SOIC, TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- -- Symbol VOUT, VOUTA VIN-, VINA- VIN+, VINA+ VDD VINB+ VINB- VOUTB VOUTC VINC- VINC+ VSS VIND+ VIND- VOUTD NC EP Description Analog Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) No Internal Connection Exposed Thermal Pad (EP); must be connected to VSS. 2x3 TDFN 6 2 3 7 -- -- -- -- -- -- 4 -- -- -- 1, 5, 8 9 3.1 Analog Outputs 3.3 Power Supply Pins The output pins are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents. The positive power supply (VDD) is 3.5V to 16V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts can be used in single-supply operation or dual-supply operation. Also, VDD will need bypass capacitors. 3.4 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). (c) 2011 Microchip Technology Inc. DS22243C-page 15 MCP6H01/2/4 NOTES: DS22243C-page 16 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 4.0 APPLICATION INFORMATION VDD D1 V1 MCP6H0X V2 D2 VOUT The MCP6H01/2/4 family of op amps is manufactured using Microchip's state-of-the-art CMOS process and is specifically designed for low-power, high-precision applications. 4.1 4.1.1 Inputs PHASE REVERSAL The MCP6H01/2/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-36 shows the input voltage exceeding the supply voltage without any phase reversal. FIGURE 4-2: Inputs. Protecting the Analog 4.1.2 INPUT VOLTAGE LIMITS A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS); See Figure 2-38. In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see Section 1.1 "Absolute Maximum Ratings "). The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors against many (but not all) over-voltage conditions, and to minimize the input bias current (IB). VDD Bond Pad 4.1.3 INPUT CURRENT LIMITS In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see Section 1.1 "Absolute Maximum Ratings "). Figure 4-3 shows one approach to protecting these inputs. The resistors R1 and R2 limit the possible currents in or out of the input pins (and the ESD diodes, D1 and D2). The diode currents will go through either VDD or VSS. VDD D1 D2 MCP6H0X VOUT Bond VIN+ Pad Input Stage Bond VIN- Pad V1 R1 V2 R2 R3 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > VSS Bond Pad FIGURE 4-1: Structures. Simplified Analog Input ESD The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go well above VDD; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow over-voltage (beyond VDD) events. Very fast ESD events (that meet the specification) are limited so that damage does not occur. In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; Figure 4-2 shows one approach to protecting these inputs. FIGURE 4-3: Inputs. 4.1.4 Protecting the Analog NORMAL OPERATION The inputs of the MCP6H01/2/4 op amps connect to a differential PMOS input stage. It operates at a low common mode input voltage (VCM), including ground. With this topology, the device operates with a VCM up to VDD - 2.3V and 0.3V below VSS (refer to Figure 2-3 through 2-5). The input offset voltage is measured at VCM = VSS - 0.3V and VDD - 2.3V to ensure proper operation. (c) 2011 Microchip Technology Inc. DS22243C-page 17 MCP6H01/2/4 For a unity gain buffer, VIN must be maintained below VDD - 2.3V for correct operation. 1000 1k Recommended R ISO () VDD = 16V RL = 10 k 4.2 Rail-to-Rail Output The output voltage range of the MCP6H01/2/4 op amps is 0.020V (typical) and 14.980V (typical) when RL = 10 k is connected to VDD/2 and VDD = 15V. Refer to Figures 2-24 through 2-29 for more information. 100 GN: 1 V/V 2 V/V 5 V/V 10 4.3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. While a unity-gain buffer (G = +1V/V) is the most sensitive to capacitive loads, all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = + 1V/V), a small series resistor at the output (RISO in Figure 4-4) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will generally be lower than the bandwidth with no capacitance load. 1 10p 100p 1n 10n 0.1 1 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 Normalized Load Capacitance; CL/GN (F) FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high-frequency performance. It can use a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. 4.5 Unused Op Amps - VIN MCP6H0X + RISO VOUT CL FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. Figure 4-5 gives the recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., -1V/V gives GN = +2V/V). After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6H01/2/4 SPICE macro model are very helpful. An unused op amp in a quad package (MCP6H04) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. Circuit A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. 1/4 MCP6H04 (A) VDD R1 R2 VDD VREF 1/4 MCP6H04 (B) VDD R2 V REF = VDD x -------------------R1 + R2 FIGURE 4-6: Unused Op Amps. DS22243C-page 18 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 4.6 PCB Surface Leakage 4.7 4.7.1 Application Circuits DIFFERENCE AMPLIFIER In applications where low input bias current is critical, PCB surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low-humidity conditions, a typical resistance between nearby traces is 1012. A 15V difference would cause 15 pA of current to flow; which is greater than the MCP6H01/2/4 family's bias current at +25C (10 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. The MCP6H01/2/4 op amps can be used in current sensing applications. Figure 4-8 shows a resistor (RSEN) that converts the sensor current (ISEN) to voltage, as well as a difference amplifier that amplifies the voltage across the resistor while rejecting common mode noise. R1 and R2 must be well matched to obtain an acceptable Common Mode Rejection Ratio (CMRR). Moreover, RSEN should be much smaller than R1 and R2 in order to minimize the resistive loading of the source. To ensure proper operation, the op amp common mode input voltage must be kept within the allowed range. The reference voltage (VREF) is supplied by a low-impedance source. In single-supply applications, VREF is typically VDD/2. . Guard Ring VIN- VIN+ VSS R1 R2 VREF VDD FIGURE 4-7: for Inverting Gain. 1. Example Guard Ring Layout RSEN ISEN MCP6H01 VOUT 2. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. R1 R2 RSEN << R1, R2 R2 VOUT = ( V1 - V 2 ) ----- + V REF R 1 FIGURE 4-8: High Side Current Sensing Using Difference Amplifier. (c) 2011 Microchip Technology Inc. DS22243C-page 19 MCP6H01/2/4 4.7.2 TWO OP AMP INSTRUMENTATION AMPLIFIER 4.7.3 PHOTODETECTOR AMPLIFIER The MCP6H01/2/4 op amps are well suited for conditioning sensor signals in battery-powered applications. Figure 4-9 shows a two op amp instrumentation amplifier using the MCP6H02, which works well for applications requiring rejection of common mode noise at higher gains. To ensure proper operation, the op amp common mode input voltage must be kept within the allowed range. The reference voltage (VREF) is supplied by a lowimpedance source. In single-supply applications, VREF is typically VDD/2. RG VREF R1 R2 R2 R1 VOUT 1/2 MCP6H02 V1 R 1 2R1 V OUT = ( V1 - V 2 ) 1 + ----- + -------- + VREF R2 RG 1/2 MCP6H02 Light ID1 - D1 MCP6H01 + VOUT = ID1*R2 The MCP6H01/2/4 op amps can be used to easily convert the signal from a sensor that produces an output current (such as a photo diode) into voltage (a trans-impedance amplifier). This is implemented with a single resistor (R2) in the feedback loop of the amplifiers shown in Figure 4-10. The optional capacitor (C2) sometimes provides stability for these circuits. A photodiode configured in Photovoltaic mode has a zero voltage potential placed across it. In this mode, the light sensitivity and linearity is maximized, making it best suited for precision applications. The key amplifier specifications for this application are: low input bias current, common mode input voltage range (including ground), and rail-to-rail output. C2 R2 VOUT VDD V2 FIGURE 4-9: Two Op Amp Instrumentation Amplifier. To obtain the best CMRR possible, and not limit the performance by the resistor tolerances, set a high gain with the RG resistor. FIGURE 4-10: Photodetector Amplifier. DS22243C-page 20 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 5.0 DESIGN AIDS 5.4 Microchip provides the basic design tools needed for the MCP6H01/2/4 family of op amps. Analog Demonstration and Evaluation Boards 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6H01/2/4 op amp is available on the Microchip web site at www.microchip.com. The model was written and tested in PSPICE owned by Orcad (Cadence). For other simulators, it may require translation. The model covers a wide aspect of the op amp's electrical specifications. Not only does the model cover voltage, current and resistance of the op amp, but it also covers the temperature and noise effects on the behavior of the op amp. The model has not been verified outside the specification range listed in the op amp data sheet. The model behaviors under these conditions cannot be guaranteed to match the actual op amp performance. Moreover, the model is intended to be an initial design tool. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site: www.microchip.com/analogtools. Some boards that are especially useful include: * MCP6XXX Amplifier Evaluation Board 1 * MCP6XXX Amplifier Evaluation Board 2 * MCP6XXX Amplifier Evaluation Board 3 * MCP6XXX Amplifier Evaluation Board 4 * Active Filter Demo Board Kit * 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2 * 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV 5.5 Application Notes 5.2 FilterLab(R) Software Microchip's FilterLab software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 MAPS (Microchip Advanced Part Selector) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/maps, MAPS is an overall selection tool for Microchip's product portfolio that includes analog, memory, MCUs and DSCs. Using this tool, you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for data sheets, purchases and sampling of Microchip parts. The following Microchip analog design note and application notes are available on the Microchip web site at www.microchip.com/appnotes, and are recommended as supplemental reference resources. * ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 * AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 * AN723: "Operational Amplifier AC Specifications and Applications", DS00723 * AN884: "Driving Capacitive Loads With Op Amps", DS00884 * AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 * AN1177: "Op Amp Precision Design: DC Errors", DS01177 * AN1228: "Op Amp Precision Design: Random Noise", DS01228 * AN1297: "Microchip's Op Amp SPICE Macro Models"' DS01297 * AN1332: "Current Sensing Circuit Concepts and Fundamentals"' DS01332 These application notes and others are listed in: * "Signal Chain Design Guide", DS21825 (c) 2011 Microchip Technology Inc. DS22243C-page 21 MCP6H01/2/4 NOTES: DS22243C-page 22 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 6.0 6.1 PACKAGING INFORMATION Package Marking Information 8-Lead SOIC (150 mil) (MCP6H01, MCP6H02) XXXXXXXX XXXXYYWW NNN Example: MCP6H01E e3 SN^^ 1103 256 8-Lead 2x3 TDFN (MCP6H01, MCP6H02) XXX YWW NN Example: AAL 103 25 14-Lead SOIC (150 mil) (MCP6H04) Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN MCP6H04 e3 E/SL^^ 1103256 14-Lead TSSOP (MCP6H04) Example: XXXXXXXX YYWW NNN 6H04E/ST 1103 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2011 Microchip Technology Inc. DS22243C-page 23 MCP6H01/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22243C-page 24 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2011 Microchip Technology Inc. DS22243C-page 25 MCP6H01/2/4 /HDG 3ODVWLF 6PDOO 2XWOLQH 61 1DUURZ PP %RG\ >62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS22243C-page 26 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2011 Microchip Technology Inc. DS22243C-page 27 MCP6H01/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22243C-page 28 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 /HDG 3ODVWLF 'XDO )ODW 1R /HDG 3DFNDJH 01 [[ PP %RG\ >7')1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ (c) 2011 Microchip Technology Inc. DS22243C-page 29 MCP6H01/2/4 /HDG 3ODVWLF 6PDOO 2XWOLQH 6/ 1DUURZ PP %RG\ >62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 b h 3 e h c A A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E 0,1 0,//,0(7(56 120 %6& %6& %6& %6& 5() 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS22243C-page 30 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ (c) 2011 Microchip Technology Inc. DS22243C-page 31 MCP6H01/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22243C-page 32 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2011 Microchip Technology Inc. DS22243C-page 33 MCP6H01/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22243C-page 34 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 APPENDIX A: REVISION HISTORY Revision C (March 2011) The following is the list of modifications: 1. 2. Added new device MCP6H04. Updated Table 3-1 with MCP6H04 pin names and details. Revision B (October 2010) The following is the list of modifications: 1. Updated Section 4.1 "Inputs". Revision A (March 2010) * Original Release of this Document. (c) 2011 Microchip Technology Inc. DS22243C-page 35 MCP6H01/2/4 NOTES: DS22243C-page 36 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range /XX Package Examples: a) b) c) Single Op Amp Single Op Amp (Tape and Reel) (SOIC and 2x3 TDFN) Dual Op Amp Dual Op Amp (Tape and Reel) (SOIC and 2x3 TDFN) Quad Op Amp Quad Op Amp (Tape and Reel) (SOIC and TSSOP) d) e) f) g) h) i) j) MCP6H01-E/SN: MCP6H01T-E/SN: MCP6H01T-E/MNY: MCP6H02-E/SN: MCP6H02T-E/SN: MCP6H02T-E/MNY: MCP6H04-E/SL: MCP6H04T-E/SL: MCP6H04-E/ST: MCP6H04T-E/ST: 8LD SOIC pkg Tape and Reel, 8LD SOIC pkg Tape and Reel, 8LD 2x3 TDFN pkg 8LD SOIC pkg Tape and Reel, 8LD SOIC pkg Tape and Reel 8LD 2x3 TDFN pkg 14LD SOIC pkg Tape and Reel, 14LD SOIC pkg 14LD SOIC pkg Tape and Reel, 14LD TSSOP pkg Device: MCP6H01: MCP6H01T: MCP6H02: MCP6H02T: MCP6H04: MCP6H04T: Temperature Range: Package: E = -40C to +125C MNY * SN = SL = ST = = Plastic Dual Flat, No Lead, (2x3 TDFN) 8-lead Lead Plastic Small Outline (150 mil Body), 8-lead Plastic Small Outline, (150 mil Body), 14-lead Plastic Thin Shrink Small Outline (150 mil Body), 14-lead * Y = Nickel palladium gold manufacturing designator. Only available on the TDFN package. (c) 2011 Microchip Technology Inc. DS22243C-page 37 MCP6H01/2/4 NOTES: DS22243C-page 38 (c) 2011 Microchip Technology Inc. MCP6H01/2/4 Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-946-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2011 Microchip Technology Inc. DS22243C-page 39 Worldwide Sales and Service AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 02/18/11 DS22243C-page 40 (c) 2011 Microchip Technology Inc. |
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